1. Field
Example Embodiments relate to a capacitance trimming circuit of a semiconductor device and/or an operation method thereof, and for example, to a capacitance trimming circuit of a semiconductor device having vertically stacked capacitor layers and an operation method thereof.
2. Description of Related Art
An analog-to-digital converter (ADC) or a digital-to-analog converter (DAC) employs a capacitance trimming circuit in order to achieve capacitance matching or correct an RC time constant. A conventional capacitance trimming circuit includes a capacitor array unit including a plurality of capacitors which are arranged in an array and a switch control logic unit including a plurality of switches to control the capacitors of the capacitor array unit. The switches of the switch control logic unit are arranged to respectively correspond to the capacitors of the capacitor array unit. The conventional capacitance trimming circuit selects one of the capacitors arranged in the capacitor array unit according to a desired, or alternatively, a predetermined capacitance using the corresponding switch of the switch control logic unit.
In the conventional capacitance trimming circuit, metal-insulator-metal (MIM) capacitors or polysilicon-insulator-polysilicon (PIP) capacitors are used as the capacitors arranged in the capacitor array unit. A conventional MIM capacitor includes a lower metal electrode and an upper metal electrode, which are stacked on a semiconductor substrate, and an interlayer insulating layer interposed between the upper and lower metal electrodes. If the capacitor array unit includes the MIM capacitors, the MIM capacitors are formed using an additional mask process other than a process used for fabricating a semiconductor device, so that the entire process becomes more complicated. Because an additional MIM capacitor or PIP capacitor for redundancy is required, a chip size may increase. The conventional capacitance trimming circuit includes the switches that are arranged in an array to select one of the capacitors arranged in the capacitor array unit, so that the area of the capacitance trimming circuit may increase.